VHDL is an IEEE [1] VHSIC [2] Hardware Description Language which is a very powerful tool. VHDL is specifically tailored to designing circuits at both, behavioural and gate levels. Although it may be possible to use VHDL to program general purpose software, this is not the purpose of the language. The very structure of the language suggests hardware design. Every integrated circuit can be described on a very realistic basis, including hierarchical design and timing problems. There are several reasons for the use of VHDL:
Besides this VHDL offers some advantages compared to other hardware description languages.
It is a common opinion that VHDL is a complex and therefore difficult language. The following chapters try to outline that VHDL is complex in its abilities, but that it's easy to learn the basic ideas of VHDL. After reading through this brief introduction and the tutorial put on the web you should have enough information to get quickly started using VHDL. The web-tutorial will help you making effective use of the language for applications in electronic design.
The beginnings of VHDL are in the early 1980's. The Department of Defence (DoD) was looking for computer language to document electronic systems with the aim to support the state-of-art in silicon technology. They wanted the design descriptions to be computer readable and executable. The primary attribute of VHDL was to reduce the on-going costs (about the half of the total costs) of operating military electronic systems. The main emphasis was the possibility of an easy and well structured description of complex circuits as well as flexibility when using different models.
In July 1983 three companies (Intermetics, IBM, Texas Instruments) got the order to develop the new language.The first version of VHDL (version 7.2) was released in August 1985.
IEEE Standard 1076-1987
In 1986 VHDL was given to the IEEE-committee to become a standard. VHDL was officially designated in 1987 as IEEE 1076-1987 standard. So far it is the only existing standard for hardware description languages. There are no other vendor independent languages that VHDL must compete against. Although the Verilog language has extensive support it began as vendor specific. This is one reason for the strong support of VHDL by industry.
Since September 1988 all electronic suppliers of the DoD have to provide VHDL-descriptions of their components.
IEEE-Standard 1164
There are some aspects in VHDL that are not implemented in the IEEE 1076-1987 standard. For this reason some simulator companies started to enhance VHDL with new features (especially new signal types). This caused some problems, because VHDL was not longer compatible with all simulation environments
IEEE-Standard 1076-1993
Due to this fact and due to the fact that an IEEE standard has to be revised every five years the new standard IEEE 1076-1993 was defined in the middle of 1993. The new hardware description language VHDL has found world-wide acceptability and has a lot of supporters. By now it has overtaken all other hardware description languages, like Verilog HDL or UDL/I.
The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standard gates. With increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASICs or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new design practices it would be impossible to handle the new complexity.
The desired design-style of all designers is the top-down design. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are a `meet in the middle of the street' design, implementing some key elements of both design styles.
Figure 1 shows a Top-Down design approach.
Figure 1: Top -Down Design Approach
VHDL supports a design at many different levels of abstraction. Three of them are very important:
This level describes a system by concurrent algorithms. Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other. Functions, procedures and processes are the main elements. There is no regard to the structural realisation of the design.
Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing possibility, operations are scheduled to occur at certain times.
Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `low', `high', `undefined', `true', `false', etc.). The usable operations are predefined (AND, NAND, OR, NOR, XOR, NOT, etc.).
Usually a VHDL-Model consists of three parts: an entity, an architecture and one or more configurations. Sometimes also packages are used and testbenches must be written to test models.
An entity declaration in VHDL is a statement that defines the external specification of a circuit or sub-circuit. Using the information provided in an entity declaration (the port names and the data type and direction of each port), you have all the information you need to connect that portion of a circuit into other, higher-level circuits, or to design input stimulus for testing purposes. The actual operation of the circuit, however, is not included in the entity declaration.
A very simple example is a nand gate (see Figure 2).
Figure 2: Schematic and Entity of a Nand Gate
At the top of the example is a library clause (LIBRARY IEEE;) and a use clause (USE IEEE.std_logic_1164.ALL;).This gives the entity access to all names declared within package STD_LOGIC_1164 in the library IEEE. The entity declaration includes the name of the entity and a set of generic and port declarations. GENERICS are constants passed into components, usually counts or delays. The PORT statement allows to define system I/O. A port may correspond to a pin on a IC, an edge connector on a board, etc. The following are signal types which can be declared in the port statement:
IN | Input to the system |
OUT | Output from the system |
INOUT | A bi-directional SIGNAL |
BUFFER | A register attached to an output. (It is normally impossible to read an output, but a buffer allows this.) |
The generic is defined with type time because it is a delay value of 5 ns, although it is possible to pass in any VHDL type.
The second part of a VHDL-model is the architecture declaration. Every entity declaration you write must be accompanied by at least one corresponding architecture. VHDL allows you to create more than one alternate architecture for each entity. An architecture declaration consists of zero or more declarations (of items such as intermediate signals, components that will be referenced in the architecture, local functions and procedures and constants) followed by a begin statement and a series of concurrent statements. The name of the architecture body is just an arbitrary label invented by the user. Within an architecture all statements are concurrent. There are two commonly used approaches for an architecture description, structural and behavioural. Figure 3 gives an example of how a complete system can be build hierarchically by combining structural and behavioural models.
Figure 3: Example of a Hierarchical VHDL-Model
A behavioural model is one which defines the behaviour of a system, how a system acts. The used statements are PROCESS, WAIT, IF, CASE, FOR-LOOP. The nand gate from above can be described in a behavioural model as follows:
Architecture of a Nand Gate
The architecture contains a concurrent signal assignment which describes the function of the design entity. The concurrent assignment executes, whenever one of the ports a or b changes its value. The order in which concurrent signals are written has no effect on their execution. The signal assignment from the example has a delay, that means that the signal on the left hand side is updated after the given delay.
As already mentioned a structural model can be many levels deep, starting with primitive gates and building to describe a complete system. A RS-Flip Flop can be constructed from the simple nand gate above, as can be seen in figure 4.
Figure 4: Structural Description of a RS-FlipFlop
The Flip Flop is defined as two interconnected nand gate instantiations. These are defined in separate VHDL code. This allows to use different levels in coding. For example, it would be possible to instantiate the RS-FF component to form a shift register. It is necessary that the ports in a component declaration match the ports in the entity declaration one for one. The names, order, mode and types of the ports to be used are defined in the component declaration. A component has to be declared only once within an architecture, but may be instanced several times. (Two times in this example).
The next type of design unit available in VHDL is called a configuration declaration. A configuration can be thought of as being roughly analogous to a parts list for a design. It specifies, which architectures are to be bound to which entities. This allows to have different architectures bound to an entity statement and to change how components are connected in a design description at the time of simulation or synthesis. Configurations are optional, the VHDL standard specifies a set of rules that provide you with a default configuration, e. g. if you have provided more than one architecture for an entity, the last architecture compiled will take precedence and will be bound to the entity.
A package is used to collect commonly used declarations for use globally among different design units. It is identified by the PACKAGE keyword and can consist of two parts, a package declaration and an optional package body. Packages allow convenient ways of defining functions and constants which are used in more than one VHDL programs. They can be thought of as being a common storage area. Items defined within a package can be made visible to any other design unit in the complete VHDL design. They also can be compiled into libraries for later use.
Packages act like an ENTITY, they declare the interfaces to the functions and subprograms found in the package body. The following gives some of the possible types of statements:
Packages defining one or more deferred constants or containing declarations of subprograms require a package body additionally. The relationship between a package and package body is similar to the relationship between an entity and its architecture. Like an architecture a package body must have the same name as its corresponding package declaration.
One of the most important tasks is testing a design description. The only way to verify a VHDL model to see if it operates as expected is to simulate it. Simulators usually offer a built in test capability, but usually it is more desirable to actually construct a VHDL test process. The easiest way to understand the concept of a test bench is to think of it as a virtual tester circuit. This circuit, which is described in VHDL, applies stimulus to your design description. The tested VHDL-model is called device under test (dut).
Figure 5: Testbench
The Data Source can be a FSM producing waveforms or stored waveframes. The observer is optional . The observing process can be manual (WAVEVIEW) or a comparison with stored waveforms.
VHDL contains many types of data structures. All VHDL objects have a type associated with them. The most common data types are listed below:
The primary means by which sequential operations can be described is the PROCESS. Processes are the basic unit of behavioural descriptions. A process is considered a series of sequential statements which represents a single action during simulation. A process is executed until a wait statement or the end of the process is reached. All statements within a process are sequential, the execution time of a process can be thought of as zero. This means that multiple processes can be executed in parallel with little or no concern for which processes complete their operations first (concurrent execution). Figure 6 shows the general structure of a process.
Figure 6: Structure of a PROCESS
A process statement consists of an optional process name, the PROCESS keyword, an optional sensitivity list, an optional declaration section (e. g. for variables), a BEGIN keyword, a sequence of sequential statements and an END statement. The sensitivity list is required if the process doesn't contain a wait-statement, otherwise the process would be permanently executed and hinder the execution of any other statements. A process with a sensitivity list is only executed when one of the signals in the sensitivity list changes.